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ISL6571
Data Sheet April 18, 2005 FN9082.4
Complementary MOSFET Driver and Synchronous Half-Bridge Switch
The Intersil ISL6571 provides a new approach for implementing a synchronous rectified buck switching regulator. The ISL6571 replaces two power MOSFETs, a Schottky diode, two gate drivers and synchronous control circuitry. Its main applications address high-density power conversion circuits including multiphase-topology computer microprocessor core power regulators, ASIC and memory array regulators, etc. Another useful feature of the ISL6571 is the compatibility with three-state input control: left open, the PWM input turns off both output drives. The ISL6571 operates in continuous conduction mode reducing EMI constraints and enabling high bandwidth operation.
Features
* Improved Performance over Conventional Synchronous Buck Converter using Discrete Components * Optimal Deadtime Provided by Adaptive Shoot-Through * Switching Frequency up to 1MHz - High-Bandwidth, Fast Transient Response - Small, Low Profile Converters * Reduced Connection Parasitics between Discrete Components - Low Electromagnetic Emissions * Low Profile, Low Thermal Impedance Packaging - High Power Density Applications * QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile * Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER ISL6571CR* ISL6571CRZ* (See Note) ISL6571EVAL1 TEMP. RANGE (C) 0 to 70 0 to 70 PACKAGE PKG. DWG. # 68 Ld 10x10 QFN L68.10x10A 68 Ld 10x10 QFN L68.10x10A (Pb-free)
Applications
* Multiphase Power Regulators * Low-Voltage Switchmode Power Conversion * High-Density Power Converters
Evaluation Board
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6571 Pinout
PGND PGND PGND PGND PGND
ISL6571 (QFN) TOP VIEW
PHASE LGATE1 PGND PVCC GND LGATE 53 PGND PGND PGND VCC NC NC 52 51 50 71 GND 49 48 47 46 45 69 PHASE 44 43 42 41 70 VIN 40 39 38 37 36 28 29 30 31 32 33 19 20 21 22 23 24 25 26 27 34 35
68
67
66
65
64
63
62
61
60
59
58
56
57
55
54
PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE
1 2 3 4 5 6 7 8 9
NC GND NC PWM BOOT GND PHASE VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN
10 11 12 13 14 15 16 18 NC 17
PHASE
NC
NC
NC
NC
NC
NC
NC
NC
VIN
NC
VIN
VIN
VIN
VIN
2
VIN
FN9082.4
VCC
PVCC
VIN
POWER-ON RESET (POR) BOOT
10K PWM
10K
+
-
3
FN9082.4
DRIVE1
UFET
ISL6571
5V
CONTROL LOGIC
GATE CONTROL PVCC
PHASE
LGATE DRIVE2
LFET
GND
LGATE1
PGND
FIGURE 1. BLOCK DIAGRAM
ISL6571
+12VIN +5VIN CBOOT LOUT PWM CONTROL AND DRIVERS VOUT COUT
ISL6571
FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM
LIN +12VIN +5VIN VCC PWM PVCC BOOT VIN + CIN1 CBOOT1
U2 ISL6571
LGATE1 LGATE 20 VCC 18 17 PWM4 ISEN4 PWM1 ISEN1 15 16 VCC PWM PVCC BOOT VIN + CIN2 GND PHASE
LOUT1
PGND
RSNS1
CBOOT2
POWER GOOD
PWM2 19 PGOOD ISEN2
14 13
U3 ISL6571
LGATE1 LGATE GND PHASE
LOUT2 VOUT
U1 HIP6301
COUT PGND RSNS2
+
8 RFS
FS/DIS
PWM3 ISEN3 COMP
11 12
5 4 3 2 1
VID0 VID1 VID2 VID3 VID4 GND 9
6 C2 C1
VCC PWM
PVCC
BOOT VIN
+
CIN3 CBOOT3
FB VSEN 10
7
R2
U4 ISL6571
LGATE1 LGATE GND PHASE
LOUT3
ROFFSET
PGND
RSNS3
R1
FIGURE 3. TYPICAL APPLICATION
4
FN9082.4
ISL6571
Absolute Maximum Ratings
Bias Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V Driver Supply, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V Conversion Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . VCC+0.3V DRIVE1 Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . .+15V Input Voltage, PWM . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 7V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1)
JC (C/W)
Recommended Operating Conditions
Control and Conversion Voltage, VCC, VIN. . . . . . . . . . +12V 10% MOSFET Bias Supply, PVCC . . . . . . . . . . . . . . . . . . . +5V to +10V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0C to 70C Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0C to 125C
Pad 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Pad 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 Pad 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Maximum Storage Temperature Range . . . . . . . . . . . -40C to 125C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JC is measured with the component mounted on a typical application PCB. A separate JC value is provided for each of the three exposed die pads (#69, 70, 71). Each value should be used in combination with the power dissipated by only the individual die mounted on that pad.
Electrical Specifications
PARAMETER SUPPLY CURRENT Nominal Bias Supply Current POWER-ON RESET Rising VCC Threshold VCC Threshold Hysteresis MOSFET DRIVER Input Impedance PWM Rising Threshold PWM Falling Threshold
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC
PWM Open
-
2.5
3.6
mA
9.70 -
9.95 2.40
10.40 -
V V
ZIN
1.30
5 80 56 230
3.80 3.40 -
k V V ns ns V ns
PWM-to-PHASE Low-to-High Propagation Delay PWM-to-PHASE High-to-Low Propagation Delay Shutdown Window Shutdown Holdoff Time UPPER MOSFET (UFET) Drain-to-Source ON-State Resistance
tPLH tPHL
1.60
tSH
-
rDS(ON)
VBOOT - VPHASE = 5V VBOOT - VPHASE = 10V
12.8 7.70 25
13.5 9.20 -
18.2 12.7 -
m m A
ON-State Drain Current LOWER MOSFET (LFET) Drain-to-Source ON-State Resistance rDS(ON)
VBOOT - VPHASE = 5V
VPVCC = 5V VPVCC = 10V
4.10 3.40 25
4.80 4.05 -
5.55 4.70 -
m m A
ON-State Drain Current
VPVCC = 5V
5
FN9082.4
ISL6571 Typical Performance Curves/Setup
+12V +5V CPVCC +12V CVCC VCC PVCC BOOT VIN ILOUT(p-p) CVIN NORMALIZED r(DS)ON VOUT ROUT 1.8 1.6 1.4 VGS = 10V ID = 12A
CBOOT LOUT
1.2 1.0
PWM
CONTROL AND DRIVERS ISL6571 GND PGND
VOUT ROUT
PHASE COUT
0.8 0.6 -25 0 25 75 50 Tj (C) 100 125 150
FIGURE 4. TYPICAL TEST CIRCUIT
FIGURE 5. UPPER MOSFET ON RESISTANCE vs TEMPERATURE
126 VPVCC = 5V 108 90 IPVCC (mA) 72 54 36 18 0 100 200 VPVCC = 10V IPHASE = 0A
1.26 1.08
1.6 VGS = 10V 1.4 NORMALIZED r(DS)ON ID = 20A
0.90 0.72 0.54 0.36 0.18 0 900 1000 PPVCC (W)
1.2
1.0
0.8
300 400 500 600 700 800 SWITCHING FREQUENCY (kHz)
0.6 -25 0 25 75 50 Tj (C) 100 125 150
FIGURE 6. BIAS SUPPLY CURRENT/POWER vs FREQUENCY
FIGURE 7. LOWER MOSFET ON RESISTANCE vs TEMPERATURE
4.00 VPVCC = 5V 3.50 DISSIPATED POWER (W) ILOUT = 12A DISSIPATED POWER (W) LOUT = 1H
4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50
VPVCC = 5V LOUT = 1H 12Vin/1.5Vout
750kHz 500kHz 300kHz
3.00
200kHz
2.50
2.00
1.50 200 300 600 400 500 700 800 SWITCHING FREQUENCY (kHz) 900 1000
0
0
1.5
3.0
4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 OUTPUT CURRENT (A)
FIGURE 8. ISL6571 POWER DISSIPATION vs FREQUENCY AT 12A
FIGURE 9. ISL6571 POWER DISSIPATION vs CURRENT AT 200kHz, 300kHz, 500kHz, 750kHz
6
FN9082.4
ISL6571 Typical Performance Curves/Setup (Continued)
93 91 89 87 EFFICIENCY (%) 85 83 81 79 77 75 73 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 OUTPUT CURRENT (A) 200kHz 300kHz 500kHz 750kHz
FIGURE 10. ISL6571 EFFICIENCY AT 200kHz, 300kHz, 500kHz, 750kHz
Functional Pin Descriptions
VCC (Pin 54)
Provide a 12V bias supply for the driver IC to this pin. The voltage at this pin is monitored for Power-On Reset (POR) purposes.
provides the bias for the upper MOSFET drive and the gate charge for the upper MOSFET.
LGATE (Pin 53)
This pin is the output of the lower MOSFET drive. Connect this pin to LGATE1 pin using the shortest available path.
PVCC (Pin 56)
Provide a well decoupled 5V to 10V bias supply at this pin. The voltage at this pin is used to bias the gates of the MOSFET switches.
LGATE1 (Pin 58)
This pin is connected to the gate of the lower MOSFET switch. Connect this pin to LGATE pin using the shortest available path.
GND (Pins 46, 50, 57, 71)
Ground pins for the driver IC. Connect these pins to the circuit ground (plane) and to the PGND pins using the shortest available paths.
PWM (Pin 48)
Connect this pin to the regulating controller's PWM output. Left open, this input will float to approximately 2.5V and cause both MOSFET switches to be turned off. Applying 5V to this input causes the upper MOSFET switch to be turned on. A 0V applied to this input causes the lower MOSFET switch to be turned on. The approximate input impedance of this pin is 5k.
PGND (Pins 60-68)
This is the source ground connection for the lower MOSFET switches. Connect these pins to the circuit ground (plane) and to the GND pins using the shortest available paths.
VIN (Pins 29-44, 70)
Connect these pins to the input voltage to be converted down. Provide bulk and high-frequency decoupling capacitors as close to these pins as feasible.
NC (Pins 18-26, 28, 49, 51, 52, 55)
These pins are not internally connected.
Description
Bias Requirements
The on-board driver includes a Power-On Reset (POR) function, which continually monitors the input bias supply. The POR monitors the bias voltage (+12VIN) at the VCC pin, and enables the ISL6571 for operation immediately after it exceeds the rising threshold. Upon the bias voltage's drop below the falling threshold, the IC is disabled and both internal MOSFETs are turned off. The output drivers are powered from the PVCC pin. For proper functionality and driving capability, connect PVCC to
PHASE (Pins 1-17, 27, 45, 59, 69)
As a minimum, connect pin 69 to the output inductor. The remainder of the PHASE pins may be tied to pin 69, left open, or used for other connections. It is recommended pin 45 is connected to the bootstrap capacitor, CBOOT.
BOOT (Pin 47)
This pin is connected to the PVCC pin through an internal quasi-diode. Connect a bootstrap capacitor from this pin to PHASE pin 45 (0.1F recommended). This capacitor 7
FN9082.4
ISL6571
a suitable supply, 5V to 10V, no higher than the voltage applied at the VCC pin. The higher the voltage applied at the PVCC pin, the better the channel enhancement of the onboard power MOSFETs, but also the higher the power dissipated inside the driver. The down-conversion voltage applied at VIN cannot exceed the bias voltage applied at VCC, but can be as low as practically possible. layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turn-off transition of the upper MOSFET. Prior to turn-off, the upper MOSFET was carrying the full load current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET or Schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. The ISL6571 is the first step in such an efficient design. By bringing the driver and switching transistors in close proximity, most of the interconnect/layout parasitic inductances are greatly reduced. However, these benefits are nulled if the associated decoupling elements and other circuit components are not carefully positioned and laid out to help the ISL6571 realize its full potential. Figure 12 shows one possible layout pattern, detailing preferred positioning of components, land size/pattern, and via count. Figure 12 is one of many possible layouts yielding good results; use it for general illustration and guidance. Locate the decoupling capacitors, especially the highfrequency ceramic capacitors, close to the ISL6571. To fully exploit ceramic capacitors' low equivalent series inductance (ESL), insure their ground connection is made as close to their grounded terminal as physically feasible. Figure 12 details via-in-pad (VIP) practices, where the via is placed on the component's landing pad, thus yielding the shortestpath, lowest ESL connection to the desired plane/island. Via-in-pad design is very important to the layout of the ISL6571, since it is an integral part of the thermal design consideration. VIP not only provides the lowest ESL circuit connections, but it is essential to the propagation of heat from the internal dies to the ambient. The vias placed directly underneath the bottom pads of the package provide a low thermal impedance path for the heat generated inside the IC to diffuse through the internal planes, as well as through islands on the back side of the board. Layout with landing pads for the bottom pads of the package devoid of vias is possible (rather, with vias placed outside of the package outline), but the thermal performance of such a layout would be significantly reduced. Use the smallest diameter vias available and avoid the use of thermal relief on the contacts with internal planes; if thermal relief is mandatory on all vias, design the thermal relief so that it voids the smallest possible copper area around the vias (thus preserving thermal conductivity and reducing electrical contact resistance). A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes.
FN9082.4
Operation
The ISL6571 combines two MOSFET transistors in a synchronous buck power train configuration, along with a halfbridge MOSFET driver designed to control these two MOSFETs. When reviewing the operational details, refer to Figure 5 test setup. With all requirements for operation met, a logic high signal on the PWM pin causes the UFET to turn on, while a logic low signal applied to the PWM pin causes LFET to turn on. If the PWM input is driven within the shutdown window and remains there for the minimum holdoff time specified (See `Electrical Specifications'), both MOSFETs are turned off.
PWM
GND
PHASE
GND
tPLH
FIGURE 11. PHASE RESPONSE TO PWM INPUT
At the transition between the on intervals of the two MOSFETs, the internal driver acts in a `break-before-make' fashion. Thus, the driver monitors the on device and turns on the (previously) off device, following a short time delay after the on MOSFET has turned off. This behavior is necessary to insure the absence of cross-conduction (shoot-through) amongst the two MOSFETs.
Application and Component Selection Guidelines
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component
tPHL
8
tSH
ISL6571
Use the remaining printed circuit layers for small signal wiring. The wiring traces from the surrounding application to the ISL6571 should be sized according to their task. Thus, small-signal traces, like the PWM signal or the ISEN feedback (if used in conjunction with another Intersil controller), only need be as wide as 5-10mils. Traces carrying bias current should be larger, proportionately with the current flowing through them; for example, traces carrying PVCC current around 50-100mA would require 30-50mils. Generally, the best connections are the shortest, enclosing the least amount of area possible. Similarly, from a conduction requirement perspective, where vias are required to carry current, use a via for each 2-3A of RMS current.
TO PWM CBULK TO +12V CBOOT TO +5V CVCC GND VIN
TO VIN
CPVCC PHASE
CHF (x2)
Bootstrap Requirements
The ISL6571 features an integrated boot element connected between the PVCC and BOOT pins. A 0.1F external bootstrap capacitor is recommended.
TO LOUT KEY ISLAND ON POWER PLANE LAYER CONNECTING TRACES ON TOP/BOTTOM LAYERS VIA CONNECTION TO OTHER PLANEs
Capacitor (Decoupling) Selection
To fully extract the benefits of a highly performant power integrated circuit, the circuit elements surrounding it must conform to the same high standards as the active power element. As such, the capacitors used for high-frequency decoupling of the ISL6571 should be good quality ceramic, with a low ESR and ESL (X7R, X5R dielectric, and 0805 or smaller footprints recommended); a minimum of two 1F capacitors are recommended. Bulk decoupling capacitor technology is not restricted to ceramic, as electrolytic capacitors are also suitable. For best results, select capacitors based on the input RMS current draw of the circuit, with a low ESL; distribute evenly amongst and place them as close to the ISL6571 as possible.
FIGURE 12. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
Use copper-filled polygons on the top and bottom circuit layers for the PHASE node, but do not unnecessarily oversize these particular islands. Since the PHASE node is subject to very high dV/dt voltages, the stray capacitors formed between these islands and the surrounding circuitry or internal planes will tend to couple switching noise. On the other hand, these islands have to be sufficiently large to offer a good path to surrounding environment for the heat produced inside the ISL6571.
ISL6571 DC-DC Converter Application Circuit
Figure 13 shows an application circuit of a power supply for a microprocessor computer system. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, contact Intersil to order the evaluation kit ISL6571EVAL1. Also see Intersil web page (http://www.intersil.com).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN9082.4
ISL6571
LIN +12VIN > +5VIN > VCC PWM LGATE1 PVCC BOOT VIN + CIN1 CBOOT1
U2 ISL6571
PHASE
LOUT1
LGATE2 CVCC1 LGATE GND
PGND
RSNS1
20 VCC PWM1 ISEN1 PWM2 ISEN2 POWER GOOD > PWM3 19 PGOOD 15 16 14 13 11 12 VCC PWM LGATE1 PVCC BOOT VIN + CIN2 CBOOT2
RPG
U3 ISL6571
PHASE
LOUT2
U1 HIP6301
ISEN3
LGATE2 LGATE GND
COUT PGND RSNS2
+
8 RFS
FS/DIS
PWM4 ISEN4 COMP
18 17
VOUT 5 4 3 2 1 VID0 VID1 VID2 VID3 VID4 GND 9 6 VCC PWM LGATE1 PVCC BOOT VIN + CIN3 CBOOT3
C2 C1
FB VSEN 10
7
R2
U4 ISL6571
PHASE
LOUT3
LGATE2 LGATE GND
ROFFSET
PGND
RSNS3
ADDITIONAL HIGH-FREQUENCY DECOUPLING CVCC2-5 CPVCC2-5 CVIN2-5 COUT_HF 1 to each of VCC2-5 C3 1 to each of PVCC2-5 2 to each of VIN2-5 varied HF mix to VOUT R3
R1 VCC PWM LGATE1 PVCC BOOT VIN + CIN4 CBOOT4
U5 ISL6571
PHASE
LOUT4
LGATE2 LGATE GND
varied bulk mix to VOUT COUT_BULK
PGND
RSNS3
FIGURE 13. TYPICAL ISL6571 APPLICATION CIRCUIT
10
FN9082.4
ISL6571 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X A D D/2 D1 6 INDEX AREA 1 2 3 N D1/2 2X 0.15 C B 0.15 C A
L68.10x10A
68 LEAD MICRO LEAD FRAME PLASTIC PACKAGE (CUSTOMIZED WITH THREE EXPOSED PADS) MILLIMETERS SYMBOL A A1 MIN NOMINAL 0.20 REF 0.18 0.23 10.00 BSC 9.75 BSC 7.55 2.44 4.48 7.70 2.59 4.63 10.00 BSC 9.75 BSC 7.55 2.44 4.48 7.70 2.59 4.63 0.50 BSC 0.25 0.50 0.60 68 17 17 0.60 12 0.75 7.85 2.74 4.78 7.85 2.74 4.78 0.30 MAX 0.90 0.05 0.70 NOTES 5, 8 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 8 2 3 3 Rev. 0 2/02 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5-1994. 2. N is the number of peripheral terminals. Exposed pads are terminals 69, 70 and 71, as shown. 3. Nd is the number of terminals in the X direction, and Ne is the number of terminals in the Y direction. 4. Controlling dimension: Millimeters. Angles are in degrees. 5. Dimension b applies to the plated terminal and is measured between 0.20mm and 0.25mm from the terminal tip.
E1/2
E/2
A2 A3 b
E
E1
D D1 D2 D3
0.15 C B 2X 0.15 C A 2X C SEATING PLANE A3 TOP VIEW
B
D4 E E1
A2
E2
A NX 0.05 C
E3 E4 e
SIDE VIEW
A1
NX b 4X P D4 4X P D2 D2/2 D3
5 0.10 M C A B 7 8 NX k
k L N Nd Ne P
70 69
E4 (Ne-1)Xe REF. E2
6 INDEX AREA 3 2 1 NX L N 8 e (Nd-1)Xe REF. BOTTOM VIEW
E2/2 71 7 8 E3
CC C L 5 A1 NX b C L
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a molded or marked feature. 7. Dimensions D2/3/4 and E2/3/4 are for the three exposed pads which provide improved electrical and thermal performance.
SECTION "C-C" e TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE e
8. Nominal dimensions provided to assist with PCB Land Pattern Design efforts, see Technical Brief TB389.
11
FN9082.4

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